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Brteve's API for EveApps
Version 0.0.1
The reference document for common folder of EveApps project.
 
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FlashHelper.c
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1
32#include "FlashHelper.h"
33#include "Gpu_Hal.h"
34
35/* Below are helper functions, not listed in cocmd */
36
43{
44 ft_uint32_t result;
45 ft_uint32_t transMatrix[6];
46#if defined(EVE_SUPPORT_CAPACITIVE)
48#else
50#endif
51
52 eve_printf_debug("App_CoPro_Widget_Calibrate: Start\n");
53
54 EVE_CoCmd_dlStart(phost);
55 EVE_Cmd_wr32(phost, CLEAR_COLOR_RGB(64, 64, 64));
56 EVE_Cmd_wr32(phost, CLEAR(1, 1, 1));
57 EVE_Cmd_wr32(phost, COLOR_RGB(0xff, 0xff, 0xff));
58
59 EVE_CoCmd_text(phost, (uint16_t)(phost->Width / 2), (uint16_t)(phost->Height / 2), 27, OPT_CENTER, "Please Tap on the dot");
60
61 result = EVE_CoCmd_calibrate(phost);
62 EVE_Cmd_waitFlush(phost);
63
64 eve_printf_debug("App_CoPro_Widget_Calibrate: End\n");
65
66 // Print the configured values
67 EVE_Hal_rdMem(phost, (ft_uint8_t*)transMatrix, REG_TOUCH_TRANSFORM_A, 4 * 6); //read all the 6 coefficients
68 eve_printf_debug("Touch screen transform values are A 0x%x,B 0x%x,C 0x%x,D 0x%x,E 0x%x, F 0x%x\n",
69 transMatrix[0], transMatrix[1], transMatrix[2], transMatrix[3], transMatrix[4], transMatrix[5]);
70
71 return result != 0;
72}
73
74#ifdef EVE_FLASH_AVAILABLE
91{
92 uint32_t last_chunk = (num % 4096); /* must be multiple of 4096. Cut off the extended data */
93
94 if ((dest_flash % FLASH_UPDATE_ALIGN_BYTE != 0) || ((src_ram % 4) != 0)) /* Check aligned address */
95 {
97 }
98
100 {
101 EVE_CoCmd_flashUpdate(phost, dest_flash, src_ram, FLASH_UPDATE_ALIGN_BYTE);
102 EVE_Cmd_waitFlush(phost);
103 }
104 else if (last_chunk == 0) /* num is multiple of 4k */
105 {
106 EVE_CoCmd_flashUpdate(phost, dest_flash, src_ram, num);
107 EVE_Cmd_waitFlush(phost);
108 }
109 else /* num is not fit in multiple of 4k */
110 {
111 EVE_CoCmd_flashUpdate(phost, dest_flash, src_ram, num - last_chunk);
112 EVE_Cmd_waitFlush(phost);
113
114 /* 4k is quite big for allocating new stack/heap data. So reuse the pointer and write dummy data to flash */
115 EVE_CoCmd_flashUpdate(phost, dest_flash + num - last_chunk, src_ram + num - last_chunk, FLASH_UPDATE_ALIGN_BYTE);
116 EVE_Cmd_waitFlush(phost);
117 }
118 return FLASH_CMD_SUCCESS;
119}
120#endif
121
122#ifdef EVE_FLASH_AVAILABLE
137Flash_Cmd_Status_t FlashHelper_Read(EVE_HalContext* phost, uint32_t dest_ram, uint32_t src_flash, uint32_t num, uint8_t *read_data)
138{
139 num = num - (num % 4); /* Only read lesser or equal aligned bytes */
140
141 if ((src_flash % FLASH_READ_ALIGN_BYTE != 0) || ((dest_ram % 4) != 0)) /* Check aligned address */
142 {
144 }
145
146 EVE_CoCmd_flashRead(phost, dest_ram, src_flash, num);
147 EVE_Cmd_waitFlush(phost);
148
149 EVE_Hal_rdMem(phost, read_data, dest_ram, num);
150 return FLASH_CMD_SUCCESS;
151}
152#endif
153
154#ifdef EVE_FLASH_AVAILABLE
162{
164 EVE_Cmd_waitFlush(phost);
165}
166#endif
167
168#ifdef EVE_FLASH_AVAILABLE
176{
177 return EVE_Hal_rd8(phost, REG_FLASH_STATUS);
178}
179#endif
180
181#ifdef EVE_FLASH_AVAILABLE
190{
192 EVE_Cmd_waitFlush(phost);
193}
194#endif
195
196/*
197
198*/
199#ifdef EVE_FLASH_AVAILABLE
213Flash_Cmd_Status_t FlashHelper_Write(EVE_HalContext* phost, uint32_t dest_flash, uint32_t num, const uint8_t* write_data)
214{
215 uint8_t padding_arr[FLASH_WRITE_ALIGN_BYTE]; /* write_data must be 256-byte aligned */
216 uint32_t aligned_length = num % FLASH_WRITE_ALIGN_BYTE;
217
218 if (dest_flash % FLASH_WRITE_ALIGN_BYTE != 0) /* Check aligned address */
219 {
221 }
222
223 if (aligned_length == 0) /* write_data is already aligned */
224 {
225 FlashHelper_flashWriteExt(phost, dest_flash, num, write_data);
226 EVE_Cmd_waitFlush(phost);
227 }
228 else
229 {
230 /* Write first aligned chunks of write_data */
231 if (num - aligned_length > 0)
232 {
233 FlashHelper_flashWriteExt(phost, dest_flash, num - aligned_length, write_data);
234 EVE_Cmd_waitFlush(phost);
235 }
236 /* Write the rest write_data */
237 write_data = write_data + num - aligned_length;
238 for (uint32_t i = 0; i < FLASH_WRITE_ALIGN_BYTE; i++)
239 {
240 if (i < aligned_length)
241 {
242 padding_arr[i] = *write_data++;
243 }
244 else
245 {
246 padding_arr[i] = 0xFF; /* Should use 0xFF instead of 0x00 to avoid writing overhead */
247 }
248 }
249 FlashHelper_flashWriteExt(phost, dest_flash + num - aligned_length, FLASH_WRITE_ALIGN_BYTE, padding_arr);
250 EVE_Cmd_waitFlush(phost);
251 }
252 return FLASH_CMD_SUCCESS;
253}
254#endif
255
256/*
257
258*/
259#ifdef EVE_FLASH_AVAILABLE
276{
277 uint32_t ret = 0;
278 //uint8_t read_data[CMD_FIFO_SIZE]; Debug only
279 uint8_t curr_flash_state = EVE_Hal_rd8(phost, REG_FLASH_STATUS);
280 uint16_t ret_addr = 0;
281 if (curr_flash_state == nextState) {
282 return ret;
283 }
284
285 //Only handle if nextState is diff
286 if (FLASH_STATUS_DETACHED == nextState)
287 {
289 EVE_Cmd_waitFlush(phost);
290 }
291 else if (FLASH_STATUS_BASIC == nextState)
292 {
293 if (FLASH_STATUS_FULL == curr_flash_state)
294 {
295 do
296 {
298 EVE_Cmd_waitFlush(phost);
300 }
302 EVE_Cmd_waitFlush(phost);
303 }
304 else if (FLASH_STATUS_FULL == nextState)
305 {
306 if (FLASH_STATUS_BASIC != curr_flash_state)
307 {
308 do
309 {
311 EVE_Cmd_waitFlush(phost);
313 }
314 EVE_CoCmd_flashFast(phost, 0);
315 EVE_Cmd_waitFlush(phost);
316
317 /* Read the return code in CMD_BUFFER */
318 ret_addr = (EVE_Cmd_wp(phost) - 4) & FIFO_SIZE_MASK;
319 ret_addr = (ret_addr + 3) & FIFO_BYTE_ALIGNMENT_MASK; //4 byte alignment
320
321 ret = EVE_Hal_rd32(phost, RAM_CMD + ret_addr);
322 }
323 else
324 {
325 ret = 0xffff;
326 }
327
328 return ret;
329}
330#endif
331
332#ifdef EVE_FLASH_AVAILABLE
340{
341 uint8_t val;
342 /* Try detaching and attaching the flash followed by fast mdoe */
344 EVE_Cmd_waitFlush(phost);
345 val = EVE_Hal_rd8(phost, REG_FLASH_STATUS);
346
347 if (FLASH_STATUS_DETACHED != val)
348 {
349 printf("Error, Flash is not able to detatch %d\n", val);
350 return 0;
351 }
352
354 EVE_Cmd_waitFlush(phost);
355 val = EVE_Hal_rd8(phost, REG_FLASH_STATUS);
356
357 if (FLASH_STATUS_BASIC != val)
358 {
359 printf("Error, Flash is not able to attach %d\n", val);
360 return 0;
361 }
362
363 EVE_CoCmd_flashFast(phost, 0);
364 EVE_Cmd_waitFlush(phost);
365 val = EVE_Hal_rd8(phost, REG_FLASH_STATUS);
366
367 if (FLASH_STATUS_FULL != val)
368 {
369 printf("Error, Flash is not able to get into full mode, status: %d\n", val);
370 return 0;
371 }
372 return 1;
373}
374#endif
375
376#if (EVE_SUPPORT_CHIPID >= EVE_BT817)
386 uint32_t eve_W = phost->Width;
387 uint32_t eve_H = phost->Height;
388 uint32_t logical_W = eve_H * physical_W / physical_H;
389
390 // Configure panel
391 EVE_Hal_wr32(phost, REG_HSIZE, logical_W);
392 EVE_CoCmd_hsf(phost, eve_W);
393}
394#endif /* EVE_SUPPORT_CHIPID >= EVE_BT817 */
395
396#ifdef EVE_FLASH_AVAILABLE
409{
410 uint32_t send_data32 = 0;
411
412 EVE_Cmd_startFunc(phost);
414 EVE_Cmd_wr32(phost, dest);
415 EVE_Cmd_wr32(phost, num);
416 for (uint32_t i = 0; i < num; i = i + 4)
417 {
418 /* Pack 4 bytes into a 32-bit data each sending package */
419 send_data32 = *data++;
420 send_data32 |= (*data++) << 8;
421 send_data32 |= (*data++) << 16;
422 send_data32 |= (*data++) << 24;
423 EVE_Cmd_wr32(phost, send_data32);
424 }
425 EVE_Cmd_endFunc(phost);
426}
427#endif
428
429/*************************************************************************************************
430* DL buffer functions
431**************************************************************************************************/
433
434#ifdef BUFFER_OPTIMIZATION
435uint8_t DlBuffer[EVE_DL_SIZE];
436#endif
437
445{
446#ifdef BUFFER_OPTIMIZATION
447 /* Copy the command instruction into buffer */
448 uint32_t* pBuffcmd;
449 /* Prevent buffer overflow */
450 if (DlBuffer_Index < DL_SIZE)
451 {
452 pBuffcmd = (uint32_t*)&DlBuffer[DlBuffer_Index];
453 *pBuffcmd = cmd;
454 }
455 else
456 {
457 printf("DlBuffer overflow\n");
458 }
459#else
461#endif
462 /* Increment the command index */
464}
465
472{
473#ifdef BUFFER_OPTIMIZATION
474 if (DlBuffer_Index > 0)
475 EVE_Hal_wrMem(phost, RAM_DL, DlBuffer, DlBuffer_Index); /* Not legal on big endian CPU */
476#endif
477 DlBuffer_Index = 0;
478}
479
486{
487 DlBuffer_Index = index;
488}
489
497void GPU_DLSwap(Gpu_Hal_Context_t* phost, uint8_t DL_Swap_Type)
498{
499 uint8_t Swap_Type = DLSWAP_FRAME;
500 uint8_t Swap_Done = DLSWAP_FRAME;
501
502 if (DL_Swap_Type == DLSWAP_LINE)
503 {
504 Swap_Type = DLSWAP_LINE;
505 }
506
507 /* Perform a new DL swap */
508 EVE_Hal_wr8(phost, REG_DLSWAP, Swap_Type);
509
510 /* Wait till the swap is done */
511 while (Swap_Done)
512 {
513 Swap_Done = EVE_Hal_rd8(phost, REG_DLSWAP);
514
515 if (DLSWAP_DONE != Swap_Done)
516 {
517 EVE_sleep(10);//wait for 10ms
518 }
519 }
520}
521
528{
529 for (int8_t i = 100; i >= 0; i -= 3)
530 {
531 EVE_Hal_wr8(phost, REG_PWM_DUTY, i);
532 EVE_sleep(2);//sleep for 2 ms
533 }
534}
535
543{
544 for (int8_t i = 0; i <= 100; i += 3)
545 {
546 EVE_Hal_wr8(phost, REG_PWM_DUTY, i);
547 EVE_sleep(2);//sleep for 2 ms
548 }
549 /* Finally make the PWM 100% */
550 uint8_t i = 128;
551 EVE_Hal_wr8(phost, REG_PWM_DUTY, i);
552}
553
563void Fifo_Init(Fifo_t* pFifo, uint32_t StartAddress, uint32_t Length, uint32_t HWReadRegAddress, uint32_t HWWriteRegAddress)
564{
565 /* update the context parameters */
566 pFifo->fifo_buff = StartAddress;
567 pFifo->fifo_len = Length;
568 pFifo->fifo_rp = pFifo->fifo_wp = 0;
569
570 /* update the hardware register addresses - specific to FT800 series chips */
571 pFifo->HW_Read_Reg = HWReadRegAddress;
572 pFifo->HW_Write_Reg = HWWriteRegAddress;
573}
574
582{
583 pFifo->fifo_rp = EVE_Hal_rd32(host, pFifo->HW_Read_Reg);
584}
585
595uint32_t Fifo_Write(Gpu_Hal_Context_t* host, Fifo_t* pFifo, const uint8_t* buffer, uint32_t NumbytetoWrite)
596{
597 uint32_t FreeSpace = Fifo_GetFreeSpace(host, pFifo);
598 uint32_t TotalBytes = NumbytetoWrite;
599
600 if (NumbytetoWrite > FreeSpace)
601 {
602 /* update the read pointer and get the free space */
603 Fifo_Update(host, pFifo);
604 FreeSpace = Fifo_GetFreeSpace(host, pFifo);
605
606 if (NumbytetoWrite > FreeSpace)
607 {
608 TotalBytes = FreeSpace;
609 }
610 }
611
612 /* sanity check */
613 if (TotalBytes <= 0)
614 {
615 return 0;//error condition
616 }
617 /* check for the loopback conditions */
618 if ((pFifo->fifo_wp + (int32_t)TotalBytes) >= pFifo->fifo_len)
619 {
620 uint32_t partialchunk = pFifo->fifo_len - pFifo->fifo_wp;
621 uint32_t secpartialchunk = TotalBytes - partialchunk;
622
623 EVE_Hal_wrMem(host, pFifo->fifo_buff + pFifo->fifo_wp, buffer, partialchunk);
624 if (secpartialchunk > 0)
625 {
626 EVE_Hal_wrMem(host, pFifo->fifo_buff, buffer + partialchunk, secpartialchunk);
627 }
628 pFifo->fifo_wp = secpartialchunk;
629
630 }
631 else
632 {
633 EVE_Hal_wrMem(host, pFifo->fifo_buff + pFifo->fifo_wp, buffer, TotalBytes);
634 pFifo->fifo_wp += TotalBytes;
635 }
636
637 /* update the write pointer address in write register */
638 EVE_Hal_wr32(host, pFifo->HW_Write_Reg, pFifo->fifo_wp);
639
640 return TotalBytes;
641}
642/***************************************************************************
643* Interface Description : FIFO related apis
644* write and wait for the fifo to be empty. handle cases even if
645* the Numbytes are more than freespace
646* Implementation :
647* Return Value : void
648* Author :
649****************************************************************************/
650
659void Fifo_WriteWait(Gpu_Hal_Context_t* host, Fifo_t* pFifo, const uint8_t* buffer, uint32_t Numbyte)
660{
661 uint32_t TotalBytes = Numbyte;
662 uint32_t currchunk = 0;
663 uint32_t FreeSpace;
664 const uint8_t* pbuff = buffer;
665 /* blocking call, manage to check for the error case and break in case of error */
666 while (TotalBytes > 0)
667 {
668 currchunk = TotalBytes;
669 FreeSpace = Fifo_GetFreeSpace(host, pFifo);
670 if (currchunk > FreeSpace)
671 {
672 currchunk = FreeSpace;
673 }
674
675 Fifo_Write(host, pFifo, pbuff, currchunk);
676 pbuff += currchunk;
677 TotalBytes -= currchunk;
678
679 }
680}
681
689void Fifo_Write32(Gpu_Hal_Context_t* host, Fifo_t* pFifo, uint32_t WriteWord)
690{
691 Fifo_WriteWait(host, pFifo, (uint8_t*)&WriteWord, 4);
692}
693
702{
703 uint32_t FreeSpace = 0;
704
705 Fifo_Update(host, pFifo);
706
707 if (pFifo->fifo_wp >= pFifo->fifo_rp)
708 {
709 FreeSpace = pFifo->fifo_len - pFifo->fifo_wp + pFifo->fifo_rp;
710 }
711 else
712 {
713 FreeSpace = pFifo->fifo_rp - pFifo->fifo_wp;
714 }
715
716 if (FreeSpace >= 4)
717 {
718 FreeSpace -= 4;//make sure 1 word space is maintained between rd and wr pointers
719 }
720 return FreeSpace;
721}
722
724{
725 uint8_t status = Gpu_Hal_Rd8(phost, REG_FLASH_STATUS);
726
727 if (status == FLASH_STATUS_DETACHED)
728 {
730 App_Flush_Co_Buffer(phost);
732 status = Gpu_Hal_Rd8(phost, REG_FLASH_STATUS);
733
734 if (FLASH_STATUS_BASIC != status)
735 {
736 printf("Error, Flash is not able to attach\n");
737 return -1;
738 }
739 }
740 int32_t size = Gpu_Hal_Rd32(phost, REG_FLASH_SIZE);
741
742 return size;
743}
744/* Nothing beyond this */
EVE_HAL_EXPORT void EVE_Cmd_startFunc(EVE_HalContext *phost)
Begin writing a function, keeps the transfer open.
Definition EVE_Cmd.c:262
EVE_HAL_EXPORT void EVE_Cmd_endFunc(EVE_HalContext *phost)
End writing a function, closes the transfer.
Definition EVE_Cmd.c:274
EVE_HAL_EXPORT uint16_t EVE_Cmd_wp(EVE_HalContext *phost)
Write to Coprocessor.
Definition EVE_Cmd.c:80
EVE_HAL_EXPORT bool EVE_Cmd_wr32(EVE_HalContext *phost, uint32_t value)
Write 4 bytes to Coprocessor's command fifo.
Definition EVE_Cmd.c:394
EVE_HAL_EXPORT uint32_t EVE_CoCmd_calibrate(EVE_HalContext *phost)
Send CMD_CALIBRATE.
Definition EVE_CoCmd.c:500
EVE_HAL_EXPORT uint32_t EVE_CoCmd_flashAttach(EVE_HalContext *phost)
Attach flash.
static void EVE_CoCmd_clearCache(EVE_HalContext *phost)
Send CMD_CLEARCACHE.
Definition EVE_CoCmd.h:244
static void EVE_CoCmd_flashErase(EVE_HalContext *phost)
Send CMD_FLASHERASE.
Definition EVE_CoCmd.h:644
EVE_HAL_EXPORT void EVE_CoCmd_text(EVE_HalContext *phost, int16_t x, int16_t y, int16_t font, uint16_t options, const char *s,...)
Send CMD_TEXT.
EVE_HAL_EXPORT uint32_t EVE_CoCmd_flashFast(EVE_HalContext *phost, uint32_t *result)
Enter fast flash state.
#define EVE_CoCmd_hsf(phost, hsf)
Definition EVE_CoCmd.h:351
static void EVE_CoCmd_flashRead(EVE_HalContext *phost, uint32_t dest, uint32_t src, uint32_t num)
Read from Flash to RAM_G. Call EVE_Cmd_waitFlush to wait for completion.
Definition EVE_CoCmd.h:679
static void EVE_CoCmd_dlStart(EVE_HalContext *phost)
Send CMD_DLSTART.
Definition EVE_CoCmd.h:159
static void EVE_CoCmd_flashDetach(EVE_HalContext *phost)
Send CMD_FLASHDETACH.
Definition EVE_CoCmd.h:715
static void EVE_CoCmd_flashUpdate(EVE_HalContext *phost, uint32_t dest, uint32_t src, uint32_t num)
Send CMD_FLASHUPDATE. This command must be followed by the data to write.
Definition EVE_CoCmd.h:704
#define DLSWAP_DONE
#define CTOUCH_MODE_COMPATIBILITY
#define DLSWAP_LINE
#define REG_HSIZE
#define CLEAR(c, s, t)
#define REG_DLSWAP
#define ADC_DIFFERENTIAL
#define REG_TOUCH_ADC_MODE
#define RAM_CMD
#define COLOR_RGB(red, green, blue)
#define FLASH_STATUS_BASIC
#define REG_FLASH_SIZE
#define FLASH_STATUS_FULL
#define RAM_DL
Definition EVE_GpuDefs.h:95
#define OPT_CENTER
#define DLSWAP_FRAME
#define REG_CTOUCH_EXTENDED
#define CMD_FLASHWRITE
#define REG_PWM_DUTY
#define REG_TOUCH_TRANSFORM_A
#define FLASH_STATUS_DETACHED
#define CLEAR_COLOR_RGB(red, green, blue)
#define EVE_DL_SIZE
Definition EVE_GpuDefs.h:56
#define REG_FLASH_STATUS
EVE_HAL_EXPORT uint32_t EVE_Hal_rd32(EVE_HalContext *phost, uint32_t addr)
Read 4 bytes from Coprocessor's memory.
Definition EVE_Hal.c:189
EVE_HAL_EXPORT void EVE_Hal_rdMem(EVE_HalContext *phost, uint8_t *result, uint32_t addr, uint32_t size)
Read a block data from Coprocessor's memory.
Definition EVE_Hal.c:206
EVE_HAL_EXPORT void EVE_Hal_wr8(EVE_HalContext *phost, uint32_t addr, uint8_t v)
Write 8 bits to Coprocessor's memory.
Definition EVE_Hal.c:220
EVE_HAL_EXPORT void EVE_Hal_wr32(EVE_HalContext *phost, uint32_t addr, uint32_t v)
Write 4 bytes to Coprocessor's memory.
Definition EVE_Hal.c:248
EVE_HAL_EXPORT void EVE_Hal_wrMem(EVE_HalContext *phost, uint32_t addr, const uint8_t *buffer, uint32_t size)
Write a buffer to Coprocessor's memory.
Definition EVE_Hal.c:263
EVE_HAL_EXPORT uint8_t EVE_Hal_rd8(EVE_HalContext *phost, uint32_t addr)
Read 8 bits from Coprocessor's memory.
Definition EVE_Hal.c:157
EVE_HAL_EXPORT void EVE_sleep(uint32_t ms)
Sleep in milisecond.
unsigned short uint16_t
int int32_t
unsigned int uint32_t
unsigned char uint8_t
signed char int8_t
#define eve_printf_debug(fmt,...)
static ft_uint32_t ft_uint8_t * buffer
Definition FT_Gpu_Hal.h:139
#define ft_void_t
Definition FT_Gpu_Hal.h:57
#define FIFO_BYTE_ALIGNMENT_MASK
Definition FT_Gpu_Hal.h:72
#define ft_uint32_t
Definition FT_Gpu_Hal.h:54
#define FIFO_SIZE_MASK
Definition FT_Gpu_Hal.h:71
static ft_void_t ft_uint32_t * cmd
Definition FT_Gpu_Hal.h:184
#define ft_uint8_t
Definition FT_Gpu_Hal.h:50
#define ft_bool_t
Definition FT_Gpu_Hal.h:62
void fadein(EVE_HalContext *phost)
Fadein animation perform display fadein effect by changing the display PWM from 0 till 100 and finall...
ft_bool_t Esd_Calibrate(EVE_HalContext *phost)
Do calibration.
Definition FlashHelper.c:42
uint32_t Fifo_Write(Gpu_Hal_Context_t *host, Fifo_t *pFifo, const uint8_t *buffer, uint32_t NumbytetoWrite)
write and update the write register
int32_t FlashHelper_GetSizeMB(Gpu_Hal_Context_t *phost)
void App_WrDl_Buffer(Gpu_Hal_Context_t *phost, uint32_t cmd)
Write DL command to buffer.
ft_void_t Ft_Gpu_HorizontalScanoutFilter(EVE_HalContext *phost, uint32_t physical_W, uint32_t physical_H)
Adjust for non-sqare pixel panel.
void Fifo_Update(Gpu_Hal_Context_t *host, Fifo_t *pFifo)
update both the read and write pointers
uint32_t DlBuffer_Index
void GPU_DLSwap(Gpu_Hal_Context_t *phost, uint8_t DL_Swap_Type)
API to check the status of previous DLSWAP and perform DLSWAP of new DL Check for the status of previ...
void App_Set_DlBuffer_Index(uint32_t index)
Set DL buffer index.
void fadeout(EVE_HalContext *phost)
Fadeout animation.
void Fifo_WriteWait(Gpu_Hal_Context_t *host, Fifo_t *pFifo, const uint8_t *buffer, uint32_t Numbyte)
write and wait for the fifo to be empty. handle cases even if the Numbytes are more than freespace
void App_Flush_DL_Buffer(const Gpu_Hal_Context_t *phost)
Flush DL buffer to Coprocessor.
uint32_t Fifo_GetFreeSpace(Gpu_Hal_Context_t *host, Fifo_t *pFifo)
get the free space in the fifo
void Fifo_Init(Fifo_t *pFifo, uint32_t StartAddress, uint32_t Length, uint32_t HWReadRegAddress, uint32_t HWWriteRegAddress)
Init mediafifo.
void Fifo_Write32(Gpu_Hal_Context_t *host, Fifo_t *pFifo, uint32_t WriteWord)
write one word and update the write register
Eve's connected flash helper functions.
ft_void_t FlashHelper_flashWriteExt(EVE_HalContext *phost, uint32_t dest, uint32_t num, const uint8_t *data)
ft_void_t FlashHelper_ClearCache(EVE_HalContext *phost)
uint32_t FlashHelper_SwitchFullMode(EVE_HalContext *phost)
ft_void_t FlashHelper_Erase(EVE_HalContext *phost)
Flash_Cmd_Status_t FlashHelper_Read(EVE_HalContext *phost, uint32_t dest_ram, uint32_t src_flash, uint32_t num, uint8_t *read_data)
Flash_Cmd_Status_t FlashHelper_Write(EVE_HalContext *phost, uint32_t dest_flash, uint32_t num, const uint8_t *write_data)
uint32_t FlashHelper_SwitchState(EVE_HalContext *phost, uint8_t nextState)
uint8_t FlashHelper_GetState(EVE_HalContext *phost)
Flash_Cmd_Status_t FlashHelper_Update(EVE_HalContext *phost, uint32_t dest_flash, uint32_t src_ram, uint32_t num)
#define Gpu_CoCmd_FlashAttach
Definition Gpu_CoCmd.h:71
void EVE_Cmd_waitFlush(EVE_HalContext *host)
Definition Gpu_Hal.cpp:775
This file defines the generic APIs of phost access layer for the FT800 or EVE compatible silicon....
#define Gpu_Hal_Rd32
Definition Gpu_Hal.h:206
#define CMD_SIZE
Definition Gpu_Hal.h:77
#define FLASH_READ_ALIGN_BYTE
Definition Gpu_Hal.h:420
Flash_Cmd_Status_t
Definition Gpu_Hal.h:413
@ FLASH_CMD_SUCCESS
Definition Gpu_Hal.h:414
@ FLASH_CMD_ALIGNED_ERR
Definition Gpu_Hal.h:415
#define Gpu_Hal_WaitCmdfifo_empty
Definition Gpu_Hal.h:240
#define FLASH_WRITE_ALIGN_BYTE
Definition Gpu_Hal.h:418
#define FLASH_UPDATE_ALIGN_BYTE
Definition Gpu_Hal.h:419
#define Gpu_Hal_Context_t
Definition Gpu_Hal.h:134
#define App_Flush_Co_Buffer(phost)
Definition Gpu_Hal.h:439
#define Gpu_Hal_Rd8
Definition Gpu_Hal.h:204
uint32_t Height
uint32_t fifo_buff
Definition Gpu_Hal.h:154
uint32_t HW_Write_Reg
Definition Gpu_Hal.h:161
int32_t fifo_len
Definition Gpu_Hal.h:155
int32_t fifo_wp
Definition Gpu_Hal.h:156
uint32_t HW_Read_Reg
Definition Gpu_Hal.h:160
int32_t fifo_rp
Definition Gpu_Hal.h:157